Addition and Subtraction
add), and immediate (
addi), and subtract (
sub) cause exceptions on overflow. MIPS detects overflow with an exception (or interrupt ), which is an unscheduled procedure call. The address of current instruction is saved and the computer jumps to predefined address to invoke the appropriate routine for that exception.
MIPS uses exception program counter (EPC) to contain the address of the instruction that causes the exception. The instruction move from system control (
mfc0) is used to copy EPC into a general-purpose register.
Add unsigned (
addu), add immediate unsigned (
addiu), and subtract unsigned (
subu) do not cause exceptions on overflow. Programmers can trap overflow anyway: when overflow occurs, the sign bit of the result is not properly set. Compairing with sign bits of operands, the sign bit of the result can be determined.
SIMD (single instruction, multiple data): By partitioning the carry chains within a 64-bit adder, a processor could perform simultaneous operations on a short vecters of eight 8-bit operands, four 16-bit operands, etc. Vectors and 8-bit data often appears in multimedia routine.